As computers and computer processors increase in performance, memory access performance becomes a significant factor affecting overall system performance. If an interface that communicates data between a memory device and a memory controller or other application device operates slower than a processor can use data, the interface can reduce the data processing capacity of the entire computer.
For dynamic random access memory (DRAM) devices, which are commonly used as the main working memory for a computer, various interconnect technologies have been developed over the years. One such interconnect technology is used for synchronous DRAMs, or SDRAMs, which utilize a source synchronous interface, where the source of data during a memory transfer is relied upon to provide a clock signal, often referred to as a data strobe signal (DQS), that is used by a target for the data to capture such data as it is being transferred over a data line to the target. In particular, the capture of data on a data line is typically latched by the rising or falling edge of the DQS signals, for example, so that the value transmitted on a data line when the data strobe signal transitions from low to high, or visa-versa, will be latched into a data latch in the target.
Double data rate (DDR) memory elements contain multiple buses. A command and address bus is formed by a number of signals, such as, for example, a column-address strobe (CAS), row-address strobe (RAS), write enable (WE), clock enable (CKE), chip-select (CS), address (ADDR), bank address (BA) signals, and differential clock signals (CK and CKn). The data bus contains the data signals (DQ), data mask (DM) and the source synchronous strobes (DQS and DQSN). DDR3 memory elements operate with differential strobes DQS and DQSN, which enable source-synchronous data capture at twice the clock frequency. Data is registered with the rising edge of DQS and DQSN signals.
DDR3 data is transferred in bursts for both read and write operations, sending or receiving 2, 4 or 8 data words with each memory access. For read operations, data bursts of various lengths are transmitted by the DRAM device edge aligned with a strobe. For write operations, data bursts of various lengths are received by the DRAM element with a 90 degree phase-delayed strobe. The strobe signal is a bidirectional signal used to capture data. After the data is captured in the source-synchronous strobe domain, the data must be transferred into a local clock domain.
During a read operation, a host or receiving device issues a read command and communicates a clock signal to the source DRAM. After a DRAM internal delay, the DRAM returns a data signal and strobe clock signal to the host. The host uses the strobe clock signal to capture the data signal. The data signal is captured in the source-synchronous strobe domain and must be transferred into the local clock domain. The DRAM transmits a preamble on the strobe signals at the beginning of each read data burst. The preamble places the positive-true and negative-true strobe signals in a differential state to ensure that the differential strobe receiver outputs are in a valid state in preparation for the first strobe edge. The host may use the preamble period as a window in which to gate, or “unpark” the strobe receiver outputs.
However, before a preamble signal arrives at the strobe pins, i.e., when the bidirectional bus is not transferring data to the receiver, the differential inputs on the strobe receivers are driven to a termination voltage or VTT, which is ½ of VDD for DDR3 signals. When both inputs of a differential receiver are driven to the same voltage level, the output of the differential receiver depends on the input offset voltage, which typically is determined by random device mismatch and is thus undefined. Consequently, differential receiver outputs could randomly toggle because of noise on the bidirectional bus. Such output signal toggling can lead to noise on supply voltages and undesired increases in power demands.